1 of 7 040601 features accepts standard 2k x 8 or 8k x 8 cmos static rams embedded lithium energy cell retains ram data self-contained circuitry safeguards data data retention time is greater than 10 years with proper ram selection ic socket permits upgrading from 2k x 8 to 8k ram proven gas-tight socket contacts operating temperature range 0c to 70c pin assignment pin description ce - conditioned chip enable v cc - switched v cc gnd - ground all pins pass through except 20, 26 and 28. description the DS1213B smartsocket is a 28-pin, 600 mil dip socket with a built-in cmos controller circuit and an embedded lithium energy source. it accepts either 24-pin 2k x 8 (lower-justified) or 28-pin 8k x 8 jedec bytewide cmos static ram. when the socket is mated with a cmos ram, it provides a complete solution to problems associated with memory volatility. the smart-socket monitors incoming v cc for an out-of-tolerance condition. when such a condition occurs, the internal lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. using the smartsocket saves printed circuit board space since the sram/smartsocket combination occupies no more area than the sram alone. the smartsocket modifies only pins 20, 26 and 28, to nonvolatize the ram. all other pins are passed straight through. DS1213B smartsocket 16k/64k www.dalsemi.com 28-pin intelligent socket 26 v cc 3 1 2 7 9 8 6 4 5 10 12 11 13 28 v cc 27 22 20 ce 21 23 25 24 19 17 18 16 15 gnd 14
DS1213B 2 of 7 operation the DS1213B smartsocket performs five circuit functions required to battery back up a cmos memory. the first function involves switching between the battery and the v cc supply, depending on which is greater. the switch has a voltage drop of less than 0.2 volts. the second function is power-fail detection. the DS1213B constantly monitors the v cc supply. when v cc falls below 4.75 volts, a precision comparator detects the condition and inhibits the ram chip enable. the third function, write protection, is accomplished by holding the ram chip enable signal to within 0.2 volts of v cc or the battery supply whichever is greater. if the incoming chip enable signal is active at the time power fail detection occurs, write protection is delayed until after the current memory cycle is complete to avoid corruption of data. power fail detection occurs in the range of 4.75 to 4.5 volts. during nominal power supply conditions the chip enable signal will be passed through from the socket pin to the socket contact with a maximum propagation delay of 20 ns. the fourth function the DS1213B performs is to check battery status to warn of potential data loss. each time that v cc power is restored to the smartsocket the battery voltage is checked with a precision comparator. if the battery supply is less than 2.0 volts, the second memory access to the smartsocket is inhibited. battery status can, therefore, be determined by a three-step process. first, a read cycle is performed to any location in the memory, in order to save the contents of that location. a subsequent write cycle can then be executed to the same memory location, altering the data. if the next read cycle fails to verify the written data, then the battery voltage is less than 2.0v and data is in danger of being corrupted. the fifth function the smartsocket provides is battery redundancy. in many applications, data integrity is paramount. in these applications it is desirable to use two batteries to ensure reliability. the DS1213B smartsocket provides two batteries and an internal isolation switch to select between them. during battery back up, the battery with the highest voltage is selected for use. if one battery fails, the other automatically takes over. the switch between batteries is transparent to the user. a battery status warning will occur if both batteries are less than 2.0 volts. each of the two internal lithium cells has a 45 mah capacity. note: as shipped from dallas semiconductor, battery voltage cannot be measured on the v cc socket contact. only after v cc has been applied to the device for the first time and then removed will the battery voltage be present on socket contacts 28, 26 and 20.
DS1213B 3 of 7 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +7.0v operating temperature 0c to 70c storage temperature -40c to +70c soldering temperature see j-std-020a specification ? this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes pin 26 l, pin 28 l supply voltage v cc 4.75 5.0 5.5 v 1,3 logic 1 pin 20 l v ih 2.2 v cc +0.3 v 1,3 logic 0 pin 20 l v il -0.3 +0.8 v 1,3 dc electrical characteristics (0 c to 70 c; v cc = 4.75 to 5.5v) parameter symbol min typ max units notes pin 26 l, pin 28 l supply current i cc 5 ma 3,4,5 pin 26 u, pin 28 u supply voltage v cco v cc -0.2 v 1,3,8 pin 26 u, pin 28 u supply current i cco 80 ma 3,8 pin 20 l ce input leakage i il -1.0 +1.0 a 3,4 pin 20 u ce output @ 2.4v i oh -1.0 ma 2,3 pin 20 u ce output @ 4v i ol 4.0 ma 2,3 dc electrical characteristics (0 c to 70 c; v cc < 4.5v) parameter symbol min typ max units notes pin 20 output v ohl v cc -0.2 v bat- 0.2 v 1,3 pin 26 u, pin 28 u battery current i bat 1 a 3,6 pin 26 u, pin 28 u battery voltage v bat 2 3 3.6 v 1,3 capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance pin 20 l c in 5pf 3 output capacitance pin 20 u c out 7pf 3
DS1213B 4 of 7 ac electrical characteristics (0 c to 70 c; v cc = 4.75 to 5.5v) parameter symbol min typ max units notes ce propagation delay t pf 5 10 20 ns 2,9 ce high to power fall t pd 0ns ac electrical characteristics (0 c to 70 c; v cci < 4.75 v) parameter symbol min typ max units notes recovery at power -up t rec 2 80 125 ms vcc slew rate 4.75 - 4.5 v t f 300 s vcc slew rate 4.5-3 v t fb 10 s vcc slew rate 4.5-4.75 v t r 0 s ce pulse width t ce 1.5 s 7 timing diagram: power-down
DS1213B 5 of 7 timing diagram: power-up warnings: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. water washing for flux removal will discharge internal lithium source because exposed voltage pins are present. notes: 1. all voltages are referenced to ground. 2. measured with a load as shown in figure 1. 3. pin locations are designated ?u? (for upper) when a parameter definition refers to the socket receptacle and ?l? (for lower) when a parameter definition refers to the socket pin. 4. no memory inserted in the socket. 5. pin 26 l may be connected to v cc or left disconnected at the pc board. 6. i bat is the maximum load current which a correctly installed memory can use in the data retention mode and meet data retention expectations of more than 10 years at 25c. 7. t ce max. must be met to ensure data integrity on power loss. 8. v cc is within nominal limits and a memory is installed in the socket. 9. input pulse rise and fall times equal 10 ns.
DS1213B 6 of 7 output load figure 1
DS1213B 7 of 7 DS1213B intelligent socket 28 pin (for 600-mil dip) pkg 28-pin dim min max a in. mm 1.380 35.05 1.420 36.07 b in. mm 0.690 17.53 0.720 18.29 c in. mm 0.420 10.16 0.470 11.94 d in. mm 0.035 0.89 0.065 1.65 e in. mm 0.055 1.39 0.075 1.90 f in. mm 0.120 3.04 0.160 4.06 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53 l in. mm 0.380 9.65 0.420 10.67
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